The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes.
ICs are typically fabricated in and on a thin semiconductor substrate having a substantially planar surface. The source and drain regions are spaced apart impurity doped regions ion implanted into the substantially planar surface on opposite sides of the gate electrode which is formed overlying the planar surface. As the complexity of the integrated circuits increases, more and more MOS transistors are needed to implement the integrated circuit function. As more and more transistors are designed into the IC, it becomes important to shrink the size of individual MOS transistors so that the size of the IC remains reasonable and the IC can be reliably manufactured. Shrinking the size of an MOS transistor implies that the minimum feature size, that is, the minimum width of a line or the minimum spacing between lines, is reduced. MOS transistors have now been aggressively reduced to the point at which the gate electrode of the transistor is less than or equal to 90 nanometers (nm) in width. Aggressively shrinking the minimum feature size even further to incorporate more devices in and on the planar substrate surface, however, will incur a significant increase in manufacturing cost, in terms of increased capital expenditures and reduced yield.
Attempts have been made to overcome the problem of packing more and more transistors onto the semiconductor surface by manufacturing vertical transistors. In such attempts, instead of locating each of the source, drain, and channel on the substantially planar surface of the substrate, the vertical transistors are fabricated in trenches that are etched into the surface of the substrate with a source at the bottom of the trench, a drain at the top of the trench near the semiconductor surface, and a channel conducting current along the wall of the trench between the source and the drain. Unfortunately, such attempts have been largely unsuccessful because of problems of isolating one transistor from another and of making the necessary electrical contacts to the vertical transistor elements.
Accordingly, it is desirable to provide a vertical device structure that allow an increase in the number of devices integrated in an IC without requiring a further reduction in minimum feature size. In addition, it is desirable to provide a memory IC based on a vertical transistor structure. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.